1. TECHNICAL FIELD
The invention relates generally to diodes, and more specifically, to silicon-on-insulator (SOI) diode circuits.
2. BACKGROUND ART
Silicon-On-Insulator (SOI) technology, which is becoming of increasing importance in the field of integrated circuits, deals with the formation of transistors in a relatively thin layer of semiconductor material overlying a layer of insulating material. Devices formed on SOI offer many advantages over their bulk counterparts, including: higher performance, absence of latch-up, higher packing density, low voltage applications, etc. However, SOI circuits, like other electronic circuits, are: First, susceptible to electrostatic discharge (ESD), a surge in voltage (negative or positive) that occurs when a large amount of current is applied to the circuit; and second, in need of providing an ideality (a constant voltage swing of 60 mV/decade over several decades of current) for analog applications, such as in phase-locked-loop circuits, voltage regulators, and band gap reference circuits.
For ESD applications, to discharge ESD impulses, ESD protection schemes need a low voltage turn-on and a high current drive (the ability to generate or sink a large amount of current before a large amount of negative or positive voltage is developed). Traditional bulk overvoltage protection schemes, such as diode circuits, do not work well on SOI because of the presence of the SOI buried oxide. That is, conventional diodes on SOI have small current drivability because the current is carried laterally (limited by the thickness of the semiconductor material). Thus, developing a new approach or a new type of diode was necessary for adequate ESD protection for SOI circuits.
Some approaches for protecting SOI circuitry from ESD are found in the following U.S. Patents: U.S. Pat. No. 4,889,829 "Method for Producing a Semiconductor Device having a Silicon-On-Insulator Structure," issued December 1989 to Kawai; and U.S. Pat. No. 4,989,057, "ESD Protection for SOI Circuits," issued January 1991 to Lu. In the Kawai reference, ESD protection circuits, such as diodes, are made from a non-SOI substrate to protect SOI circuits. A findamental disadvantage with this approach is the circuit as disclosed in the Kawai reference creates a non-planar surface structure during fabrication, leading to many process related difficulties. For example, there would be difficulty in removing residual contaminant metal during the cleansing process, which would create large metal steps during metallization, leading to metal thing and cracking. Thus, in general, manufacturing such a circuit would not be feasible.
The Lu reference discusses a gated diode, which could be used for ESD designs. The gated diode consists of a floating-body SOI transistor, with the gate connected to a signal pad. Although the diode disclosed in the Lu reference could provide some ESD protection, the diode does not allow for the desired trait of ideal characteristics, as discussed above. Some reasons preventing ideal diode characteristics with the diode in the Lu reference and with conventional diodes in general include: 1) alignment tolerances of the substrate cause large process-induced variations; and 2) the conventional diode structure may be a polysilicon diode, which receives extension and halo implants (implants normally utilized in deep submicron MOSFETs) that degrades the ideal diode characteristics on SOI. Thus, the diode in the Lu reference may be used for ESD protection, but is not appropriate for use with analog finctions.
Accordingly, a need has developed in the art for an SOI diode that will not only provide ESD protection, but will provide compactability.